This invention relates to a method of making a metal-insulator-semiconductor (MIS) transistor having a lightly-doped drain (LDD) region.
The self-aligned gate process has commonly been used to manufacture MIS integrated circuit (IC) devices, and has remarkably miniaturized MIS transistor elements, thereby improving the performance of the MIS integrated circuit.
As the channel length is reduced to less than 1 .mu.m, the short channel effect occurs as a result of a two-dimensional potential distribution and high electric fields in the channel region. This phenomenon causes the generation of hot electrons in the channel region and entry of the hot electrons into the gate insulating layer. This varies the threshold voltage, inducing the erroneous operation of the MIS transistors.
It may be considered to decrease the voltage value of the conventional 5-volt power supply voltage. However, it is difficult to use a lowered power supply voltage, because MIS IC devices are required to have TTL logic level compatibility with bipolar IC devices and higher immunity against external noise, and it is not desired by circuit designers to increase the number of power supply.
To overcome such problems, PAUL J. TSANG et al disclosed an improved method for making MIS transistors in his paper entitled "Fabrication of High-Performance LDDFETs with Oxide Sidewall-spacer Technology", issued by IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, No. 2, APRIL 1982, p 220-226. FIG. 1 show the MIS transistor having lightly-doped drain/source regions according to the process.
In FIG. 1, the gate oxide film 12 is formed over the surface of the P-type silicon substrate 10, and the silicon gate electrode 14 is formed on the surface of the gate oxide 12. The lightly-doped N.sup.- regions 16 and 18 are formed by implanting N-type impurity ions with the use of the gate electrode 14 as a mask.
The gate wall spacers 20 and 22 are formed on the side walls of the gate electrode 14 by anisotropically etching a polycrystalline silicon layer formed by chemical vapor deposition (CVD). The heavily-doped N.sup.+ regions 24 and 26 are formed by using the sidewalls 20 and 22 as a diffusion mask.
The process described above is featured by the fact that the MIS FET having the LDD structure can be formed by using a self-alignment technique. The lightly-doped N.sup.- region 16 extending the drain region 24 functions to weaken the electric field in the channel region.
However, according to this prior art process, the lightly-doped N.sup.- region 18 extending from the source region 26 serves only as a resistance component in the channel region, resulting in a lowerd mutual conductance (gm) of the MOS FET. Also, it has been difficult to form oly the lightly-doped N.sup.- region extending from the drain region in the MIS transistor area without spoiling the advantages of the self-aligned silicon gate process.